R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 451

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

When a transfer starts, the transfer source address is added to the offset every time data is
transferred. The transfer data is written to the destination continuous addresses. When data 4 is
transferred meaning that the repeat size of transfers is completed, the transfer source address
returns to the transfer start address (address of data 1 on the transfer source) and a repeat size end
interrupt is requested. While this interrupt stops the transfer temporarily, the contents of DSAR are
written to the address of data 5 by the CPU (when the data access size is longword, write the data
1 address + 4). When the DTE bit in DMDR is set to 1, the transfer is resumed from the state when
the transfer is stopped. Accordingly, operations are repeated and the transfer source data is
transposed to the destination area (XY conversion).
Figure 10.20 shows a flowchart of the XY conversion.
Figure 10.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode
Set address and transfer count
Enable repeat escape interrupt
Decrements transfer count
and repeat size
Receives transfer request
Set repeat transfer mode
: User operation
Transfer count = 0?
Set DTE bit to 1
Transfers data
Start
End
Yes
No
: DMAC operation
Initializes transfer source address
Set transfer source address + 4
Generates repeat size end
Repeat size = 0?
interrupt request
Rev. 2.00 Oct. 21, 2009 Page 417 of 1454
Section 10 DMA Controller (DMAC)
Yes
(Longword transfer)
No
REJ09B0498-0200