R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 980

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 Serial Communication Interface (SCI, IrDA, CRC)
19.9
19.9.1
Table 19.14 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt request can activate the
DTC or DMAC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer
by the DTC or DMAC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can
activate the DTC or DMAC to allow data transfer. The RDRF flag is automatically cleared to 0 at
data transfer by the DTC or DMAC.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared to 0 simultaneously by
the TXI interrupt processing routine, the SCI cannot branch to the TEI interrupt processing routine
later.
Note that the priority order for interrupts is different between the group of SCI_0, 1, 2, and 4 and
the group of SCI_5 and SCI_6.
Table 19.14 SCI Interrupt Sources (SCI_0, 1, 2, and 4)
Rev. 2.00 Oct. 21, 2009 Page 946 of 1454
REJ09B0498-0200
Name
ERI
RXI
TXI
TEI
Interrupt Source
Receive error
Receive data full
Transmit data empty TDRE
Transmit end
Interrupt Sources
Interrupts in Normal Serial Communication Interface Mode
Interrupt Flag
ORER, FER, or PER
RDRF
TEND
DTC Activation
Not possible
Possible
Possible
Not possible
DMAC Activation
Not possible
Possible
Possible
Not possible
Priority
High
Low