R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 529

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3)
To set a negative value in EDOFR, specify a twos complement as an offset value. A twos
complement is derived by the following expression:
11.5.7
EXDMAC register values are updated as EXDMA transfer processing is performed. The updated
values depend on various settings and the transfer status. The following registers and bits are
updated: EDSAR, EDDAR, EDTCR, bits BKSZH and BKSZ in EDBSR, and bits DTE, ACT,
ERRF, ESIF and DTIF in EDMDR.
(1)
When the EDSAR address is accessed as the transfer source, the EDSAR value is output, and then
EDSAR is updated with the address to be accessed next.
Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The address is fixed
when SAT1 and SAT0 = B′00, incremented by offset register value when SAT1 and SAT0 =
B′01, incremented when SAT1 and SAT0 = B′10, and decremented when SAT1 and SAT0 =
B′11. (The increment or decrement value is determined by the data access size.)
The DTSZ1 and DTSZ0 bits in EDMDR set the data access size. When DTSZ1 and DTSZ0 =
B′00, the data is byte-size and the address is incremented or decremented by 1. When DTSZ1 and
DTSZ0 = B′01, the data is word-size and the address is incremented or decremented by 2. When
DTSZ1and DTSZ0 = B′10, the data is longword-size and the address is incremented or
decremented by 4. When a word-size or longword-size is specified but the source address is not at
the word or longword boundary, the data is divided into bytes or words for reading. When a word
or longword is divided for reading, the address is incremented or decremented by 1 or 2 according
to an actual byte-or word-size read. After a word-size or longword-size read, the address is
incremented or decremented to or from the read start address according to the setting of SAT1 and
SAT0.
Offset subtraction specification
EXDMA Source Address Register (EDSAR)
[Twos complement expression for negative offset value] = −[offset value] + 1 (−: bit reverse)
Example: Twos complement expression of H'0001FFFF
= H'FFFE0000 + H'00000001
= H'FFFE0001
A twos complement can be derived by the NEG.L instruction of the CPU.
Registers during EXDMA Transfer Operation
Rev. 2.00 Oct. 21, 2009 Page 495 of 1454
Section 11 EXDMA Controller (EXDMAC)
REJ09B0498-0200