R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 265

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 9.6 lists the number of access cycles for each interface.
Table 9.6
Basic bus interface
Byte-control SRAM interface
Burst ROM interface
Address/data multiplexed I/O
interface
DRAM
inter-
face
SDRAM
interface
[Legend]
Number enclosed by bracket: Number of access cycles
n: Pin wait (0 to ∞)
m: Number of burst accesses (0 to 63)
s: Time for a transition to or from software standby mode
Full access
Fast page
Refresh
Self-refresh
Setting mode
register
Full access
(read)
Full access
(write)
Page access
(read)
Page access
(write)
Cluster transfer
(read)
Cluster transfer
(write)
Refresh
Self-refresh
Number of access cycles in the SDRAM interface
= number of precharge cycles (1 to 4) + number of row address output cycles (1 to 4)
+ number of column address output cycles (read: 2 to 4, write: 2)
+ number of clock suspend cycles (only read: 0 or 1)
+ number of write precharge delay cycles (only write: 0 or 1)
Number of Access Cycles
=
=
=
=
=
=
=Tma
=Tma
=Tp
=
=TRp
=TRp
=
=
=
=
=
=
=
=
=
=
=
[2,3]
[2,3]
[1 to 4]
[1 to 4]
[1 to 4]
+Th
+Th
+Tr
+TRrw
+TRrw
Th
Th
Th
Th
Th
Th
Tp
Tp
Tp
Tp
Tp
TRp
TRp
[0,1]
[0,1]
[0,1]
[0,1]
[0,1]
[0,1]
[0,1]
[0,1]
[1]
[0 to 3]
[0 to 3]
[1 to 4]
[1 to 4]
[1 to 4]
[1 to 4]
[1 to 4]
[1 to 4]
[1 to 4]
+T1
+T1
+T1
+T1
+T1
+T1
+T1
+T1
+Trw
+TRr
+TRr
+Tr
+Tr
+Tr
+Tr
+Tr
+TRr
+TRr
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[0 to 3]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
+T2
+T2
+T2
+T2
+T2
+T2
+T2
+T2
+TC1
+TRc1
+
+Trw
+Trw
+Trw
+Trw
+Trw
+TRc1
+
TC1
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[0 to 3]
[0 to 3]
[0 to 3]
[0 to 3]
[0 to 3]
[1]
standby mode
standby mode
Software
Software
[1+s]
[1+s]
+Tpw
+Tpw
+Tpw
+Tpw
+Tpw
+Tpw
+TRcw
+Tc1
+Tc1
+Tc1
+Tc1
+Tc1
+TRcw
Tc1
Tc1
Tc1
Tc1
[0 to 7]
[0 to 7]
[0 to 7]
[0 to 7]
[0 to 7]
[0 to 7]
[0 to 7]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[0 to 7]
+Ttw
+Ttw
+Ttw
+Ttw
+Ttw
+Ttw
+TRc2
+Tcb
+Tcb
+TRc2
+TRc2
[n]
[n]
[n]
[n]
[n]
[n]
[1]
[0 to 31]
[0 to 31]
[1]
[1]
+T3
+T3
+T3
+T3
+Tc2
+Tc2
+TRc3
+Tcl
+Tcl
+Tcl
+Tcl
+TRc3
Rev. 2.00 Oct. 21, 2009 Page 231 of 1454
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1 to 3]
[1 to 3]
[1 to 3]
[1 to 3]
[1]
+Tt
+Tt
+Tt
+Tt
+Tt
+Tt
+Tc3
+Tc3
+TRc4
+Tsp
+Tsp
+TRp
[0,1]
[0,1]
[0,1]
[0,1]
[0,1]
[0,1]
[0,1]
[0,1]
[1]
[0,1]
[0,1]
[0 to 7]
Section 9 Bus Controller (BSC)
+Tb
+Tb
+TRp
+Tc2
+Tc2
+Tc2
+Tc2
+Tc2
+Tc2
+Tc2
+Tc2
[(1 to 8) x m]
[(1 to 8) x m]
[0 to 7]
[1]
[1]
[1]
[1]
[1]
[1]
+Tc2
[1]
[1]
[1]
+Trwl
+Trwl
+Tcb
+Tcb
[0,1]
[0,1]
[0 to 31]
[0 to 31]
REJ09B0498-0200
[(2 to 11+n)+(1 to 8) x m]
[(2 to 3)+(1 to 8) x m]
+Trwl
[0,1]
[3 to 12+n]
[3 to 12+n]
[5 to 15+n]
[4 to 18+n]
[2 to 10+n]
[5 to 18+s]
[5 to 15+s]
[4 to 17]
[4 to 11]
[5 to 14]
[4 to 11]
[5 to 44]
[3 to 36]
[4 to 41]
[2 to 33]
[4 to 14]
[2 to 4]
[2 to 4]
[4 to 7]
[3 to 6]
[2 to 3]