R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 396

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus Controller (BSC)
9.15.2
This LSI has a write data buffer function for the peripheral module access. Using the write data
buffer function enables peripheral module writes and on-chip memory or external access to be
executed in parallel. The write data buffer function is made available by setting the PWDBE bit in
BCR2 to 1. For details on the on-chip peripheral module registers, see table 9.34, Number of
Access Cycles for Registers of On-Chip Peripheral Modules in section 9.14, Internal Bus.
Figure 9.105 shows an example of the timing when the write data buffer function is used. When
this function is used, if an internal I/O register write continues for two cycles or longer and then
there is an on-chip RAM, an on-chip ROM, or an external access, internal I/O register write only
is performed in the first two cycles. However, from the next cycle onward an internal memory or
an external access and internal I/O register write are executed in parallel rather than waiting until
it ends.
Rev. 2.00 Oct. 21, 2009 Page 362 of 1454
REJ09B0498-0200
Write Data Buffer Function for Peripheral Modules
Figure 9.105 Example of Timing when Peripheral Module
Internal
address bus
Internal I/O
address bus
Internal I/O
data bus
Write Data Buffer Function is Used
Peripheral module write
Peripheral module address
On-chip
memory
read

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