R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 925

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
19.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 19.3 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and
it can be read from or written to by the CPU at all times.
Table 19.3 Relationships between N Setting in BRR and Bit Rate B
[Legend]
B:
N:
Pφ:
n and S: Determined by the SMR settings shown in the following table.
Mode
Asynchronous
mode
Clocked synchronous mode
Smart card interface mode
CKS1
0
0
1
1
Bit Rate Register (BRR)
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
SMR Setting
CKS0
0
1
0
1
ABCS Bit Bit Rate
0
1
N =
N =
N =
N =
n
0
1
2
3
64 × 2
32 × 2
8 × 2
S × 2
Pφ × 10
Pφ × 10
Pφ × 10
Pφ × 10
2n – 1
2n + 1
2n – 1
2n – 1
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
6
6
6
× B
6
× B
× B
× B
BCP1
0
0
1
1
− 1
− 1
− 1
− 1
Error
Error (%) = {
Error (%) = {
Error (%) =
Rev. 2.00 Oct. 21, 2009 Page 891 of 1454
SMR Setting
{
B × 64 × 2
B × 32 × 2
BCP0
0
1
0
1
B × S × 2
Pφ × 10
Pφ × 10
2n – 1
2n – 1
2n + 1
Pφ × 10
6
6
× (N + 1)
× (N + 1)
× (N + 1)
REJ09B0498-0200
6
S
32
64
372
256
– 1 } × 100
– 1 } × 100
– 1 × 100
}

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