R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 399

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note, however, that the bus cannot be transferred in the following cases.
• During transfer information read
• During the first data transfer
• During transfer information write back
The DTC releases the bus when the consecutive transfer cycles completed.
(3)
The DMAC sends the internal bus arbiter a request for the bus when an activation request is
generated. When the DMAC accesses an external bus space, the DMAC first takes control of the
bus from the internal bus arbiter and then requests a bus to the external bus arbiter.
After the DMAC takes control of the bus, it may continue the transfer processing cycles or release
the bus at the end of every bus cycle depending on the conditions.
The DMAC continues transfers without releasing the bus in the following case:
• Between the read cycle in the dual-address mode and the write cycle corresponding to the read
If no bus master of a higher priority than the DMAC requests the bus and the IBCCS bit in BCR2
is cleared to 0, the DMAC continues transfers without releasing the bus in the following cases:
• During 1-block transfers in the block transfer mode
• During transfers in the burst mode
In other cases, the DMAC transfers the bus at the end of the bus cycle.
(4)
The EXDMAC sends the external bus arbiter a request for the bus when an activation request is
generated. If an internal bus master accesses the external space, the bus is passed to the EXDMAC
when the bus master can release the bus. Some EXDMAC transfers are continued once it takes
control of the bus. Some EXDMAC transfers are divided and it releases the bus for each transfer
cycle.
• Transfers are continued without bus release between a read cycle and the subsequent write
• Transfers are continued without bus release in cluster transfer mode
cycle
cycle in dual address mode
DMAC
EXDMAC
Rev. 2.00 Oct. 21, 2009 Page 365 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200