R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1276

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 27 Clock Pulse Generator
27.6.2
Since various characteristics related to the resonator are closely linked to the user's board design,
thorough evaluation is necessary on the user's part, using the resonator connection examples
shown in this section as a reference. As the parameters for the resonator will depend on the
floating capacitance of the resonator and the mounting circuit, the parameters should be
determined in consultation with the resonator manufacturer. The design must ensure that a voltage
exceeding the maximum rating is not applied to the resonator pin.
27.6.3
When using the crystal resonator, place the crystal resonator and its load capacitors as close to the
XTAL and EXTAL pins as possible. Other signal lines should be routed away from the oscillation
circuit as shown in figure 27.10 to prevent induction from interfering with correct oscillation.
Rev. 2.00 Oct. 21, 2009 Page 1242 of 1454
REJ09B0498-0200
External
clock
Bus master
Notes on Resonator
Notes on Board Design
Figure 27.10 Note on Board Design for Oscillation Circuit
Inhibited
Operating clock
specified in SCKCR
CPU
Figure 27.9 Clock Modification Timing
after the bus cycle completion
C
C
One cycle (worst case)
L2
L1
CPU
Signal A Signal B
Operating clock changed
XTAL
EXTAL
This LSI
CPU

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