R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 403

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus Controller (BSC)
(10) RAS Down Mode and Software Standby Mode for DRAM Interface
When making a transition to software standby mode with the OPE bit in SBYCR set to 0 without
using the self-refresh mode, the transition should be made in RAS up mode (RCDM = 0). When
RAS down mode (RCDM = 1) is used, execute the SLEEP instruction after setting the RCDM bit
to 0. RAS down mode should be set again after recovery from software standby mode. For
SBYCR, see section 28, Power-Down Modes.
(11) RAS Down Mode and Clock Frequencies Setting for DRAM/SDRAM
Write access to SCKCR for setting the clock frequencies should be performed in RAS up mode
(RCDM = 0). When RAS down mode (RCDM = 1) is used, set the RCDM bit to 0 before writing
to SCKCR. RAS down mode should be set again after clock frequencies are set. For SCKCR, see
section 27, Clock Pulse Generator.
(12) Cluster Transfer to SDRAM Space
Cluster transfer mode is available for the SDRAM with CAS latency of 2. When the SDRAM is
used in cluster transfer mode, the SDRAM with CAS latency of 2 should be used. In cluster
transfer mode, the write-precharge output delay function by the TRWL bit is not available. The
TRWL bit must be cleared to 0.
Rev. 2.00 Oct. 21, 2009 Page 369 of 1454
REJ09B0498-0200

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