R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 453

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 DMA Controller (DMAC)
In block or repeat transfer mode, when the block or repeat size of data transfers is completed while
the block or repeat area is specified to the source address side, the source address returns to the
transfer start address and is not affected by the address update.
When the extended repeat area is specified to the source address side, operation follows the
setting. The upper address bits are fixed and is not affected by the address update.
While data is being transferred, DSAR must be accessed in longwords. If the upper word and
lower word are read separately, incorrect data may be read from since the contents of DSAR
during the transfer may be updated regardless of the access by the CPU. Moreover, DSAR for the
channel being transferred must not be written to.
(2)
DMA Destination Address Register
When the transfer destination address set in DDAR is accessed, the contents of DDAR are output
and then are updated to the next address.
The increment or decrement can be specified by bits DAT1 and DAT0 in DACR. When DAT1
and DAT0 = B'00, the address is fixed. When DAT1 and DAT0 = B'01, the address is added with
the offset. When DAT1 and DAT0 = B'10, the address is incremented. When DAT1 and DAT0 =
B'11, the address is decremented. The incrementing or decrementing size depends on the data
access size.
The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0
= B'00, the data access size is byte and the address is incremented or decremented by 1. When
DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or
decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the
address is incremented or decremented by 4. Even if the access data size of the destination address
is word or longword, when the destination address is not aligned with the word or longword
boundary, the write bus cycle is divided into byte and word cycles. While one word or one
longword of data is being written, the incrementing or decrementing size is changing according to
the actual data access size, for example, +1 or +2 for byte or word data. After the one word or one
longword of data is written, the address when the write cycle is started is incremented or
decremented by the value according to bits SAT1 and SAT0.
In block or repeat transfer mode, when the block or repeat size of data transfers is completed while
the block or repeat area is specified to the destination address side, the destination address returns
to the transfer start address and is not affected by the address update.
When the extended repeat area is specified to the destination address side, operation follows the
setting. The upper address bits are fixed and is not affected by the address update.
Rev. 2.00 Oct. 21, 2009 Page 419 of 1454
REJ09B0498-0200