R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 206

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 User Break Controller (UBC)
8.3.3
BRCRA, BRCRB, BRCRC, and BRCRD are used to specify and control conditions for channels
A, B, C, and D of the UBC.
Rev. 2.00 Oct. 21, 2009 Page 172 of 1454
REJ09B0498-0200
Bit
15
14
13
12
11
10
9
8
7
6
Initial Value:
[Legend]
n = Channels A to D
R/W:
Bit:
Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD)
Bit Name
⎯
⎯
CMFCPn
⎯
CPn2
CPn1
CPn0
⎯
⎯
⎯
R/W
15
−
0
R/W
14
−
0
CMFCPn
R/W
13
0
Initial
Value
0
0
0
0
0
0
0
0
0
0
R/W
12
−
0
CPn2
R/W
11
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CPn1
R/W
10
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Condition Match CPU Flag
UBC break source flag that indicates satisfaction of a
specified CPU bus cycle condition.
0: The CPU cycle condition for channel n break
1: The CPU cycle condition for channel n break
Reserved
These bits are always read as 0. The write value
should always be 0.
CPU Cycle Select
These bits select CPU cycles as the bus cycle break
condition for the given channel.
000: Break requests will not be generated.
001: The bus cycle break condition is CPU cycles.
01x: Setting prohibited
1xx: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
CPn0
R/W
9
0
requests has not been satisfied.
requests has been satisfied.
R/W
−
8
0
R/W
−
7
0
R/W
−
6
0
IDn1
R/W
5
0
IDn0
R/W
4
0
RWn1
R/W
3
0
RWn0
R/W
2
0
R/W
−
1
0
R/W
−
0
0