R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 151

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes: 1. For on-chip peripheral module space, see section 9, Bus Controller (BSC).
6.5.2
When an address error occurs, address error exception handling starts after the bus cycle causing
the address error ends and current instruction execution completes. The address error exception
handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the address error is generated, the
Even though an address error occurs during a transition to an address error exception handling, the
address error is not accepted. This prevents an address error from occurring due to stacking for
exception handling, thereby preventing infinitive stacking.
If the SP contents are not a multiple of 2 when an address error exception handling occurs, the
stacked values (PC, CCR, and EXR) are undefined.
Type
Data read/write EXDMAC
Single address
transfer
start address of the exception service routine is loaded from the vector table to PC, and
program execution starts from that address.
2. For the access-prohibited area, refer to figure 3.1 in section 3.4, Address Map.
Address Error Exception Handling
Bus Cycle
Bus Master
DMAC or
EXDMAC
Description
Accesses word data from even addresses
Accesses word data from odd addresses
Accesses external memory space in single-chip
mode
Accesses to access prohibited area*
Accesses external memory space
Accesses spaces other than external memory
space
Address access space is the external memory
space for single address transfer
Address access space is not the external memory
space for single address transfer
Rev. 2.00 Oct. 21, 2009 Page 117 of 1454
2
Section 6 Exception Handling
REJ09B0498-0200
Address Error
No (normal)
No (normal)
Occurs
Occurs
N0 (normal)
Occurs
No (normal)
Occurs