R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1072

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 21 I
21.3.5
ICSR confirms the interrupt request flags and status.
Rev. 2.00 Oct. 21, 2009 Page 1038 of 1454
REJ09B0498-0200
Bit
7
6
Bit
Bit Name
Initial Value
R/W
I
Bit Name
TDRE
TEND
2
C Bus Status Register (ICSR)
2
C Bus Interface 2 (IIC2)
TDRE
R/W
7
0
Initial
Value
0
0
TEND
R/W
6
0
R/W
R/W
R/W
RDRF
R/W
5
0
Description
Transmit Data Register Empty
[Setting conditions]
•
•
•
•
[Clearing conditions]
•
•
Transmit End
[Setting condition]
•
[Clearing conditions]
•
•
NACKF
When data is transferred from ICDRT to ICDRS
and ICDRT becomes empty
When the TRS bits are set
When the start (re-transmit included) condition has
been issued
When switched from reception to transmission in
slave mode
When 0 is written to this bit after reading TDRE = 1
(When the CPU is used to clear this flag by writing
0 while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When data is written to ICDRT
When the ninth clock of SCL rises while the TDRE
flag is 1
When 0 is written to this bit after reading TEND = 1
(When the CPU is used to clear this flag by writing
0 while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When data is written to ICDRT
R/W
4
0
STOP
R/W
3
0
R/W
AL
2
0
AAS
R/W
1
0
ADZ
R/W
0
0