R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 413

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
10.3.4
DTCR is a 32-bit readable/writable register that specifies the size of data to be transferred (total
transfer size).
To transfer 1-byte data in total, set H'00000001 in DTCR. When H'00000000 is set in this register,
it means that the total transfer size is not specified and data is transferred with the transfer counter
stopped (free running mode). When H'FFFFFFFF is set, the total transfer size is 4 Gbytes
(4,294,967,295), which is the maximum size. While data is being transferred, this register
indicates the remaining transfer size. The value corresponding to its data access size is subtracted
every time data is transferred (byte: −1, word: −2, and longword: −4).
Although DTCR can always be read from by the CPU, it must be read from in longwords and
must not be written to while data for the channel is being transferred.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
DMA Transfer Count Register (DTCR)
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Rev. 2.00 Oct. 21, 2009 Page 379 of 1454
Section 10 DMA Controller (DMAC)
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
REJ09B0498-0200
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0

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