R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 919

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Note:
Bit
3
2
1
0
*
Bit Name
PER
TEND
MPB
MPBT
Only 0 can be written, to clear the flag.
Initial
Value
0
1
0
0
R/W
R/(W)* Parity Error
R
R
R/W
Multiprocessor Bit Transfer
Description
Indicates that a parity error has occurred during reception
in asynchronous mode and the reception ends
abnormally.
[Setting condition]
[Clearing condition]
Transmit End
[Setting conditions]
[Clearing conditions]
Multiprocessor Bit
Stores the multiprocessor bit value in the receive frame.
When the RE bit in SCR is cleared to 0 its previous state
is retained.
Sets the multiprocessor bit value to be added to the
transmit frame.
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
When a parity error is detected during reception
Receive data when the parity error occurs is
transferred to RDR, however, the RDRF flag is not
set. Note that when the PER flag is being set to 1, the
subsequent serial reception cannot be performed. In
clocked synchronous mode, serial transmission also
cannot continue.
When 0 is written to PER after reading PER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
Even when the RE bit in SCR is cleared, the PER bit
is not affected and retains its previous value.
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a
transmit character
When 0 is written to TDRE after reading TDRE = 1
When a TXI interrupt request is issued allowing
DMAC or DTC to write data to TDR
Rev. 2.00 Oct. 21, 2009 Page 885 of 1454
REJ09B0498-0200

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