R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 96

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 CPU
Table 2.10 Branch Instructions
Rev. 2.00 Oct. 21, 2009 Page 62 of 1454
REJ09B0498-0200
Instruction
BISTZ
BFLD
BFST
Instruction
BRA/BS
BRA/BC
BSR/BS
BSR/BC
Bcc
BRA/S
JMP
BSR
JSR
RTS
RTS/L
Size
B
B
B
Size
B
B
—
—
—
—
—
—
—
Function
∼ Z → (<bit-No.> of <EAd>)
Transfers the inverse of the zero flag value to a specified bit in the
contents of a memory location. The bit number is specified by 3-bit
immediate data.
(EAs) (bit field) → Rd
Transfers a specified bit field in memory location contents to the lower bits
of a specified general register.
Rs → (EAd) (bit field)
Transfers the lower bits of a specified general register to a specified bit
field in memory location contents.
Function
Tests a specified bit in memory location contents. If the specified
condition is satisfied, execution branches to a specified address.
Tests a specified bit in memory location contents. If the specified
condition is satisfied, execution branches to a subroutine at a specified
address.
Branches to a specified address if the specified condition is satisfied.
Branches unconditionally to a specified address after executing the next
instruction. The next instruction should be a 1-word instruction except for
the block transfer and branch instructions.
Branches unconditionally to a specified address.
Branches to a subroutine at a specified address.
Branches to a subroutine at a specified address.
Returns from a subroutine.
Returns from a subroutine, restoring data from the stack to multiple
general registers.