R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 622

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Data Transfer Controller (DTC)
1. For the first transfer, set the normal transfer mode for input data. Set the fixed transfer source
2. Prepare the upper 8-bit addresses of the start addresses for 65,536-transfer units for the first
3. For the second transfer, set repeat transfer mode (with the source side as the repeat area) for re-
4. Execute the first data transfer 65536 times by means of interrupts. When the transfer counter
5. Next, execute the first data transfer the 65536 times specified for the first data transfer by
6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer,
Rev. 2.00 Oct. 21, 2009 Page 588 of 1454
REJ09B0498-0200
address, CRA = H'0000 (65,536 times), CHNE = 1, CHNS = 1, and DISEL = 0.
data transfer in a separate area (in ROM, etc.). For example, if the input buffer is configured at
addresses H'200000 to H'21FFFF, prepare H'21 and H'20.
setting the transfer destination address for the first data transfer. Use the upper eight bits of
DAR in the first transfer information area as the transfer destination. Set CHNE = DISEL = 0.
If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.
for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits
of the transfer source address for the first data transfer to H'21. The lower 16 bits of the
transfer destination address of the first data transfer and the transfer counter are H'0000.
means of interrupts. When the transfer counter for the first data transfer reaches 0, the second
data transfer is started. Set the upper eight bits of the transfer source address for the first data
transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer
and the transfer counter are H'0000.
no interrupt request is sent to the CPU.
located on the on-chip memory
Transfer information
Figure 12.16 Chain Transfer when Counter = 0
2nd data transfer
1st data transfer
information
information
Chain transfer
(counter = 0)
Upper 8 bits of DAR
Input circuit
Input buffer