R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 516

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 11 EXDMA Controller (EXDMAC)
Transfer
Address T
Address T
A
B
Total transfer
size (EDTCR)
Address B
Address B
B
A
Figure 11.8 Normal Transfer Mode Operation
(2)
Repeat Transfer Mode
In repeat transfer mode, transfer of one data access size unit is processed in response to one
transfer request. The total transfer size of up to 4 Gbytes can be set by EDTCR. The repeat size of
up to 64 Kbytes × data access size can be set by EDBSR.
The ARS1 and ARS0 bits in EDACR specify the repeat area on the source address or destination
address side. The address specified for the repeat area is restored to the transfer start address at the
end of a repeat-size transfer. This operation continues until transfer of total transfer size set in
EDTCR ends. EDTCR specified with H'00000000 is assumed as free-running mode and the repeat
transfer continues until the DTE bit in EDMDR is cleared to 0.
At the end of a repeat-size transfer, the EXDMA transfer is halted temporarily and a repeat size
end interrupt is requested to the CPU or DTC. When the RPTIE bit in EDACR is set to 1 and the
next transfer request is generated at the end of a repeat-size transfer, the ESIF bit in EDMDR is set
to 1 and the DTE bit in EDMDR is cleared to 0 to terminate the transfer. At this time, an interrupt
is requested to the CPU or DTC when the ESIE bit in EDMDR is set to 1.
The timing of EXDMA transfer including the ETEND or EDRAK output is the same as for
normal transfer mode.
Figure 11.9 shows the repeat transfer mode operation in dual address mode.
The operation without specifying a repeat area on the source or destination address side is the
same as for the normal transfer mode operation shown in figure 11.8. In this case, a repeat size end
interrupt can also be generated at the end of a repeat-size transfer.
Rev. 2.00 Oct. 21, 2009 Page 482 of 1454
REJ09B0498-0200

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