R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 137

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.2.2
RSTSR indicates the source of an internal reset or voltage monitoring interrupt.
Bit
4
3 to 0
Bit
7
Bit
Bit name
Initial value:
R/W:
Note:
*
Bit Name
LVDMON
—
Reset Status Register (RSTSR)
Bit Name
DPSRSTF
DPSRSTF
R/(W)*
To clear the flag, only 0 should be written to.
7
0
Initial Value
0
0
Initial Value
0
R/W
—
6
0
R/W
—
5
0
R/W
R
R/W
R/W
R/W*
R/W
—
4
0
Description
LVD Monitor
This bit monitors the voltage level. This bit is valid
when the LVDE bit is 1 and read as 0 when the
LVDE bit is 0. Writing to this bit is ineffective.
0: Vcc must fall below Vdet.
1: Vcc must rise above Vdet.
Reserved
These bits are always read as 0 and the write
value should always be 0.
Description
Deep Software Standby Reset Flag
This bit indicates release from deep software
standby mode due to the interrupt source
selected by DPSIER and DPSIEGR, and
generation of an internal reset.
[Setting condition]
Release from deep software standby mode due to
an interrupt source.
[Clearing condition]
•
•
voltage monitoring reset.
Writing 0 to the bit after reading it as1.
Generation of a pin reset, power on reset, or
R/W
—
3
0
Rev. 2.00 Oct. 21, 2009 Page 103 of 1454
Section 5 Voltage Detection Circuit (LVD)
Undefined
R/(W)*
LVDF
2
Undefined
R/W
—
1
REJ09B0498-0200
Undefined
PORF
R
0