R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 237

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.2.12
MPXCR specifies the address/data multiplexed I/O interface.
Bit
15
14
13
12
11
10 to 1 ⎯
0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
MPXE7
MPXE6
MPXE5
MPXE4
MPXE3
ADDEX
Address/Data Multiplexed I/O Control Register (MPXCR)
MPXE7
R/W
15
⎯
R
0
7
0
Initial
Value
0
0
0
0
0
All 0
0
MPXE6
R/W
14
⎯
R
0
6
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
MPXE5
R/W
13
⎯
R
0
5
0
Description
Address/Data Multiplexed I/O Interface Select
Specifies the bus interface for the corresponding area.
To set this bit to 1, clear the BCSELn bit in SRAMCR to
0.
0: Area n is specified as a basic interface or a byte
1: Area n is specified as an address/data multiplexed
(n = 7 to 3)
Reserved
These are read-only bits and cannot be modified.
Address Output Cycle Extension
Specifies whether a wait cycle is inserted for the
address output cycle of address/data multiplexed I/O
interface.
0: No wait cycle is inserted for the address output cycle
1: One wait cycle is inserted for the address output
control SRAM interface.
I/O interface
cycle
MPXE4
R/W
12
⎯
R
0
4
0
MPXE3
R/W
11
⎯
R
0
3
0
Rev. 2.00 Oct. 21, 2009 Page 203 of 1454
10
⎯
⎯
R
R
0
2
0
Section 9 Bus Controller (BSC)
⎯
⎯
R
R
9
0
1
0
REJ09B0498-0200
ADDEX
R/W
⎯
R
8
0
0
0