R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 354

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
(2)
Set the RCDM and BE bits in DRAMCR to 1 to make a transition to the RAS down mode. The
RCDM bit is enabled only when the BE bit is set to 1.
Even if the fast-page mode is selected, the DRAM space is not consecutively accessed and other
spaces may be accessed. The RAS signal can be held low during other space accesses. Similarly to
the DRAM RAS down mode, the READ or WRIT command can be issued without the ACTV
command. However, two DQM cycles are always inserted for a SDRAM read cycle.
Figures 9.74 and 9.75 show a timing example of RAS down mode.
The next cycle after one of the following conditions is satisfied is a full access cycle.
• When a refresh cycle is performed during RAS down mode
• When a self-refresh is performed
• When a transition to software standby mode is made
• When the external bus requested by the BREQ signal is released
• When either the RCDM or BE bit is cleared to 0
• When setting the SDRAM mode register
Some SDRAMs have a limitation on the time to hold each bank active. When such SDRAM is in
use, if the user program cannot control the time (such as software standby or sleep mode), select
the auto-refresh or self-refresh so that the given specification can be satisfied. If a refresh cycle is
not used, the user program must control the time.
Clear the RCDM bit to 0 for write access to SCKCR to set the clock frequencies. For SCKCR, see
section 27, Clock Pulse Generator.
(3)
Clear the RCDM bit in DRAMCR to 0 to set the RAS up mode.
Whenever a SDRAM space access is halted and other spaces are accessed, the next cycle is the
PALL command cycle. Only when the SDRAM space continues to be accessed, the fast-page
mode access is performed.
Rev. 2.00 Oct. 21, 2009 Page 320 of 1454
REJ09B0498-0200
RAS Down Mode
RAS Up Mode