R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 521

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.5.4
There are two bus modes: cycle steal mode and burst mode.
For auto-request activation, either cycle steal mode or burst mode can be selected by the DTF0 bit
in EDMDR. When the activation source is an external request, cycle steal mode is used.
(1)
In cycle steal mode, the EXDMAC releases the bus mastership at the end of each transfer of a
transfer unit (byte, word, longword, one block size, or one cluster size). If there is a subsequent
transfer request, the EXDMAC takes back the bus mastership, performs another transfer-unit
transfer, and then releases the bus mastership again at the end of the transfer. This procedure is
repeated until the transfer end condition is satisfied.
If a transfer request occurs in another channel during EXDMA transfer, the bus mastership is
temporarily released for another bus master, then transfer is performed on the channel for which
the transfer request was issued. For details on the operation when there are transfer requests for a
number of channels, see section 11.5.8, Channel Priority Order.
Figure 11.13 shows an example of the timing in cycle steal mode. The transfer conditions are as
follows:
• Address mode: Single address mode
• Sampling method on the EDREQ pin: Low level sensing
• CPU internal bus master is operating in external space
Cycle Steal Mode
Bus Mode
EDREQ
EDRAK
Bus cycle
Figure 11.13 Example of Timing in Cycle Steal Mode
CPU
CPU
Bus mastership returned temporarily to CPU
EXDMAC
CPU
Rev. 2.00 Oct. 21, 2009 Page 487 of 1454
Section 11 EXDMA Controller (EXDMAC)
EXDMAC
CPU
REJ09B0498-0200