R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 586

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
11.10
1. EXDMAC Register Access during Operation
2. Module Stop State
• ETENDE = 1 in EDMDR (ETEND pin enable)
• EDRAKE = 1 in EDMDR (EDRAK pin enable)
• EDACKE = 1 in EDMDR (EDACK pin enable)
3. EDREQ Pin Falling Edge Activation
Rev. 2.00 Oct. 21, 2009 Page 552 of 1454
REJ09B0498-0200
Except for clearing the DTE bit to 0 in EDMDR, settings should not be changed for a channel
in operation (including the transfer standby state). Transfer must be disabled before changing a
setting for an operational channel.
The EXDMAC operation can be enabled or disabled by the module stop control register. The
initial value is "enabled".
When the MSTPA14 bit is set to 1 in MSTPCRA, the EXDMAC clock stops and the
EXDMAC enters the module stop state. However, 1 cannot be written to the MSTPA14 bit
when any of the EXDMAC's channels is enabled for transfer, or when an interrupt is being
requested. Before setting the MSTPA14 bit, first clear the DTE bit in EDMDR to 0, then clear
the DTIF or DTIE bit in EDMDR to 0.
When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The
following EXDMAC register settings remain valid in the module stop state, and so should be
disabled, if necessary, before making the module stop transition.
Falling edge sensing on the EDREQ pin is performed in synchronization with EXDMAC
internal operations, as indicated below.
1. Activation request standby state: Waits for low level sensing on EDREQ pin, then goes to
2. Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to
3. Activation request disabled state: Waits for high level sensing on EDREQ pin, then goes to
After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is
used for the initial activation after transfer is enabled.
[2].
[3].
[1].
Usage Notes