R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 18

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.15
9.16
9.17
9.18
Section 10 DMA Controller (DMAC)............................................................... 371
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
Rev. 2.00 Oct. 21, 2009 Page xvi of xxxii
Write Data Buffer Function .............................................................................................. 361
9.15.1
9.15.2
Bus Arbitration ................................................................................................................. 363
9.16.1
9.16.2
Bus Controller Operation in Reset.................................................................................... 367
Usage Notes ...................................................................................................................... 367
Features............................................................................................................................. 371
Input/Output Pins.............................................................................................................. 374
Register Descriptions........................................................................................................ 375
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.3.8
Transfer Modes................................................................................................................. 397
Operations......................................................................................................................... 398
10.5.1
10.5.2
10.5.3
10.5.4
10.5.5
10.5.6
10.5.7
10.5.8
10.5.9
10.5.10 Bus Cycles in Dual Address Mode ................................................................... 426
10.5.11 Bus Cycles in Single Address Mode................................................................. 435
DMA Transfer End ........................................................................................................... 440
Relationship among DMAC and Other Bus Masters........................................................ 443
10.7.1
10.7.2
Interrupt Sources............................................................................................................... 445
Usage Notes ...................................................................................................................... 448
Write Data Buffer Function for External Data Bus .......................................... 361
Write Data Buffer Function for Peripheral Modules ........................................ 362
Operation .......................................................................................................... 363
Bus Transfer Timing......................................................................................... 364
DMA Source Address Register (DSAR) .......................................................... 376
DMA Destination Address Register (DDAR) .................................................. 377
DMA Offset Register (DOFR).......................................................................... 378
DMA Transfer Count Register (DTCR) ........................................................... 379
DMA Block Size Register (DBSR) .................................................................. 380
DMA Mode Control Register (DMDR)............................................................ 381
DMA Address Control Register (DACR)......................................................... 390
DMA Module Request Select Register (DMRSR) ........................................... 396
Address Modes ................................................................................................. 398
Transfer Modes................................................................................................. 402
Activation Sources............................................................................................ 407
Bus Access Modes ............................................................................................ 409
Extended Repeat Area Function ....................................................................... 411
Address Update Function using Offset ............................................................. 414
Register during DMA Transfer......................................................................... 418
Priority of Channels .......................................................................................... 423
DMA Basic Bus Cycle...................................................................................... 425
CPU Priority Control Function Over DMAC ................................................... 443
Bus Arbitration among DMAC and Other Bus Masters ................................... 444