R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 753

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
3
2
Bit Name
TGFD
TGFC
Initial
value
0
0
R/W
R/(W)* Input Capture/Output Compare Flag D
R/(W)* Input Capture/Output Compare Flag C
Description
Status flag that indicates the occurrence of TGRD input
capture or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is always
read as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is always
read as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing conditions]
•
•
When TCNT = TGRD while TGRD is functioning as
output compare register
When TCNT value is transferred to TGRD by input
capture signal while TGRD is functioning as input
capture register
When DTC is activated by a TGID interrupt while the
DISEL bit in MRB of DTC is 0
When 0 is written to TGFD after reading TGFD = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
When TCNT = TGRC while TGRC is functioning as
output compare register
When TCNT value is transferred to TGRC by input
capture signal while TGRC is functioning as input
capture register
When DTC is activated by a TGIC interrupt while the
DISEL bit in MRB of DTC is 0
When 0 is written to TGFC after reading TGFC = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
Rev. 2.00 Oct. 21, 2009 Page 719 of 1454
Section 14 16-Bit Timer Pulse Unit (TPU)
REJ09B0498-0200