R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 968

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 Serial Communication Interface (SCI, IrDA, CRC)
For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and
data is transferred with LSB-first as the start character, as shown in figure 19.26. Therefore, data
in the start character in the figure is H'3B. When using the direct convention type, write 0 to both
the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity,
which is prescribed by the smart card standard.
For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively
and data is transferred with MSB-first as the start character, as shown in figure 19.27. Therefore,
data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to
both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity,
which is prescribed by the smart card standard, and corresponds to state Z. Since the SNIV bit of
this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in
both transmission and reception.
19.7.3
Block transfer mode is different from normal smart card interface mode in the following respects.
• Even if a parity error is detected during reception, no error signal is output. Since the PER bit
• During transmission, at least 1 etu is secured as a guard time after the end of the parity bit
• Since the same data is not re-transmitted during transmission, the TEND flag is set 11.5 etu
• Although the ERS flag in block transfer mode displays the error signal status as in normal
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REJ09B0498-0200
in SSR is set by error detection, clear the PER bit before receiving the parity bit of the next
frame.
before the start of the next frame.
after transmission start.
smart card interface mode, the flag is always read as 0 because no error signal is transferred.
Block Transfer Mode
(Z)
Figure 19.27 Inverse Convention (SDIR = SINV = O/E = 1)
Ds
A
D7
Z
D6
Z
D5
A
D4
A
D3
A
D2
A
D1
A
D0
A
Dp
Z
(Z) state