R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 986

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
Rev. 2.00 Oct. 21, 2009 Page 952 of 1454
REJ09B0498-0200
output pin
output pin
SCK*
TxD
TE bit
Note: * Not output in SCI_5, 6.
Figure 19.39 Sample Flowchart for Software Standby Mode Transition during
Figure 19.40 Port Pin States during Software Standby Mode Transition
input/output
Port
Port
Cancel software standby mode
Change operating mode?
Read TEND flag in SSR
software standby mode
All data transmitted?
Make transition to
Start transmission
High output
Transmission
Initialization
(Internal Clock, Asynchronous Transmission)
TEND = 1
Yes
Yes
Yes
TE = 0
Transmission start
[2]
Start
SCI TxD output
Transmission
No
No
No
TE = 1
[1]
[3]
Transmission end
[1] Data being transmitted is lost
[2] Clear the TIE and TEIE bits to 0
[3] Setting of the module stop state
Stop
halfway. Data can be normally
transmitted from the CPU by
setting the TE bit to 1, reading
SSR, writing to TDR, and
clearing the TDRE bit to 0 after
clearing software standby mode;
however, if the DTC has been
activated, the data remaining in
the DTC will be transmitted when
both the TE and TIE bits are set
to 1.
when they are 1.
is included.
Transition to
software standby
mode
Port input/output
input/output
Port
Port
Software standby
mode canceled
High output
TxD output
SCI

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