R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 535

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.5.9
An example of the basic bus cycle timing is shown in figure 11.23. In this example, word-size
transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus
mastership is transferred from the CPU to the EXDMAC, a source address read and destination
address write are performed. The bus is not released in response to another bus request, etc.,
between these read and write operations. As like CPU cycles, EXDMAC cycles conform to the
bus controller settings.
Bφ
Address bus
EXDMAC
control
Channel 0
Channel 1
Channel 2
Bφ
Address bus
RD
LLWR
LHWR
Basic Bus Cycles
High
CPU cycle
Idle
Figure 11.23 Example of EXDMA Transfer Bus Timing
Request
held
Request
held
Request cleared
Figure 11.22 Example of Channel Priority Timing
Channel 0
Selected
Not
selected
Source address
T
1
Request
held
T
Request cleared
2
Channel 0 transfer
Channel 0
T
1
EXDMAC cycle (one word transfer)
Channel 1
Selected
T
2
Destination address
T
Request cleared
3
Channel 1 transfer
Rev. 2.00 Oct. 21, 2009 Page 501 of 1454
Section 11 EXDMA Controller (EXDMAC)
Channel 1
T
1
Channel 2
T
2
T
3
Channel 2 transfer
REJ09B0498-0200
Channel 2
CPU cycle
Idle