R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 390

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
9.13
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, the internal bus masters other than the EXDMAC continue to operate
as long as there is no external access.
In addition, in the external bus released state, the BREQO signal can be driven low to output a bus
request externally.
9.13.1
In external extended mode, when the BRLE bit in BCR1 is set to 1, and the ICR bit for the
corresponding pin is set to 1, the bus can be released to the external. Driving the BREQ pin low
issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed
timing, the BACK pin is driven low, and the address bus, data bus, and bus control signals are
placed in the high-impedance state, establishing the external bus released state. For ICR, see
section 13, I/O Ports.
In the external bus released state, the CPU, DTC, DMAC can access the internal space using the
internal bus. When any one of the CPU, DTC, DMAC, and EXDMAC attempts to accesses the
external address space, it temporarily defers initiation of the bus cycle, and waits for the bus
request from the external bus master to be canceled.
In the external bus released state, certain operations are suspended as follows until the bus request
from the external bus master is canceled:
• When a refresh is requested, refresh control is suspended.
• When the SLEEP instruction is executed to enter software standby mode or all-module clock-
• When SCKCR is written to set the clock frequencies, changing of clock frequencies is
If the BREQOE bit in BCR1is set to 1, the BREQO pin can be driven low to request cancellation
of the bus request when any of the following requests are issued.
• When any one of the CPU, DTC, DMAC, and EXDMAC attempts to access the external
• When a refresh is requested
• When a SLEEP instruction is executed to place the chip in software standby mode or all-
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REJ09B0498-0200
stop mode, control for software standby mode or all-module clock-stop mode is suspended.
suspended. For SCKCR, see section 27, Clock Pulse Generator.
address space
module-clock-stop mode
Bus Release
Operation