R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 78

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 2 CPU
2.5.4
EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0).
Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC
instructions.
For details, see section 6, Exception Handling.
Rev. 2.00 Oct. 21, 2009 Page 44 of 1454
REJ09B0498-0200
Bit
2
1
0
Bit
7
6 to 3
2
1
0
Bit Name
Z
V
C
Bit Name
T
I2
I1
I0
Extended Control Register (EXR)
Initial
Value
Undefined R/W
Undefined R/W
Undefined R/W
Initial
Value
0
All 1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 otherwise.
Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. A carry has the following types:
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
Description
Trace Bit
When this bit is set to 1, a trace exception is generated
each time an instruction is executed. When this bit is
cleared to 0, instructions are executed in sequence.
Reserved
These bits are always read as 1.
Interrupt Mask Bits
These bits designate the interrupt mask level (0 to 7).
Carry from the result of addition
Borrow from the result of subtraction
Carry from the result of shift or rotation

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