R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1129

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.7
22.7.1
Operation of the A/D converter can be disabled or enabled using the module stop control register.
The initial setting is for operation of the A/D converter to be halted. Register access is enabled by
clearing the module stop state. Set the CKS1 and CKS2 bits to 1 and clear the ADST, TRGS1,
TRGS0, and EXTRGS bits all to 0 to disable A/D conversion when entering module stop state
after operation of the A/D converter. After that, set the module stop control register after executing
a dummy read from ADCSR. For details, see section 28, Power-Down Modes.
22.7.2
When this LSI enters software standby mode with A/D conversion enabled, the analog inputs are
retained, and the analog power supply current is equal to as during A/D conversion. If the analog
power supply current needs to be reduced in software standby mode, set the CKS1 and CKS2 bits
to 1 and clear the ADST, TRGS1, TRGS0, and EXTRGS bits all to 0 to disable A/D conversion.
After that, enter software standby mode after executing a dummy read from ADCSR.
22.7.3
When the A/D start bit (ADST) is cleared during A/D conversion by software, A/D conversion
results may be stored incorrectly (ADDR), or when A/D conversion restarts, the interrupt flag may
be misset.
To avoid these events, follow the steps below.
(1)
As the ADST bit is automatically cleared when A/D conversion is completed, do not clear the bit
during A/D conversion.
(2)
• When the A/D Converter is Activated by Software
Do not clear the ADST bit during A/D conversion. To stop A/D conversion, rewrite the
SCANE bit to change modes from scan mode to single mode. By rewriting the SCANE bit, the
A/D converter is stopped without clearing the ADST bit by software.
In Single Mode or Scan Mode (One-Cycle Scan Mode)
In Scan Mode (Continuous Scan Mode)
Usage Notes
Module Stop Function Setting
A/D Input Hold Function in Software Standby Mode
Notes on Stopping the A/D Converter
Rev. 2.00 Oct. 21, 2009 Page 1095 of 1454
Section 22 A/D Converter
REJ09B0498-0200