R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 497

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
30
29
28
27
26
25, 24
Bit Name
EDACKE
ETENDE
EDRAKE
EDREQS
NRD
Initial
value
0
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
EDACK Pin Output Enable
In single address mode, enables or disables output
from the EDACK pin. In dual address mode, the
specification by this bit is ignored.
0: EDACK pin output disabled
1: EDACK pin output enabled
ETEND Pin Output Enable
Enables or disables output from the ETEND pin.
0: ETEND pin output disabled
1: ETEND pin output enabled
EDRAK Pin Output Enable
Enables or disables output from the EDRAK pin.
0: EDRAK pin output disabled
1: EDRAK pin output enabled
EDREQ Select
Selects whether a low level or the falling edge of the
EDREQ signal used in external request mode is
detected.
0: Low-level detection
1: Falling edge detection (the first transfer is detected
Next Request Delay
Selects the timing of the next transfer request to be
accepted.
0: Next transfer request starts to be accepted after
1: Next transfer request starts to be accepted after one
Reserved
They are always read as 0 and cannot be modified.
on a low level after a transfer is enabled.)
transfer of the bus cycle in progress ends.
cycle of Bφ from the completion of the bus cycle in
progress.
Rev. 2.00 Oct. 21, 2009 Page 463 of 1454
Section 11 EXDMA Controller (EXDMAC)
REJ09B0498-0200

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