R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 92

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 CPU
Note: * Only when the multiplier is available.
Rev. 2.00 Oct. 21, 2009 Page 58 of 1454
REJ09B0498-0200
Instruction
DIVU
DIVXS
DIVS
CMP
NEG
EXTU
EXTS
TAS
MAC*
CLRMAC*
LDMAC*
STMAC*
Size
W/L
B/W
W/L
B/W/L
B/W/L
W/L
W/L
B
—
—
—
—
Function
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16 bits
÷ 16 bits → 16-bit quotient, or 32 bits ÷ 32 bits → 32-bit quotient.
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
16 bits → 16-bit quotient, or 32 bits ÷ 32 bits → 32-bit quotient.
(EAd) − #IMM, (EAd) − (EAs)
Compares data between immediate data, general registers, and memory
and stores the result in CCR.
0 − (EAd) → (EAd)
Takes the two's complement (arithmetic complement) of data in a general
register or the contents of a memory location.
(EAd) (zero extension) → (EAd)
Performs zero-extension on the lower 8 or 16 bits of data in a general
register or memory to word or longword size.
The lower 8 bits to word or longword, or the lower 16 bits to longword can
be zero-extended.
(EAd) (sign extension) → (EAd)
Performs sign-extension on the lower 8 or 16 bits of data in a general
register or memory to word or longword size.
The lower 8 bits to word or longword, or the lower 16 bits to longword can
be sign-extended.
@ERd − 0, 1 → (<bit 7> of @EAd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
(EAs) × (EAd) + MAC → MAC
Performs signed multiplication on memory contents and adds the result to
MAC.
0 → MAC
Clears MAC to zero.
Rs → MAC
Loads data from a general register to MAC.
MAC → Rd
Stores data from MAC to a general register.