R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 208

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 User Break Controller (UBC)
8.4
The UBC does not detect condition matches in standby states (sleep mode, all module clock stop
mode, software standby mode, deep software standby, and hardware standby mode).
8.4.1
1. The address condition for the break is set in break address register n (BARn). A mask for the
2. The bus and break conditions are set in break control register n (BRCRn). Bus conditions
3. The condition match CPU flag (CMFCPn) is set in the event of a break condition match on the
[Legend]
n = Channels A to D
8.4.2
1. When specifying a PC break, specify the address as the first address of the required instruction.
2. The break occurs after fetching and execution of the target instruction have been confirmed. In
3. A break will not be generated even if a break before instruction execution is set in a delay slot.
4. The PC break condition is generated by specifying CPU cycles as the bus condition in break
[Legend]
n = Channels A to D
Rev. 2.00 Oct. 21, 2009 Page 174 of 1454
REJ09B0498-0200
address is set in break address mask register n (BAMRn).
consist of CPU cycle, PC break, and reading. Condition comparison is not performed when the
CPU cycle setting is CPn = B'000, the PC break setting is IDn = B'00, or the read setting is
RWn = B'00.
corresponding channel. These flags are set when the break condition matches but are not
cleared when it no longer does. To confirm setting of the same flag again, read the flag once
from the break interrupt handling routine, and then write 0 to it (the flag is cleared by writing 0
to it after reading it as 1).
If the address for a PC break condition is not the first address of an instruction, a break will
never be generated.
cases of contention between a break before instruction execution and a user maskable interrupt,
priority is given to the break before instruction execution.
control register n (BRCRn.CPn0 = 1), PC break as the break condition (IDn0 = 1), and read
cycles as the bus-cycle condition (RWn0 = 1).
Operation
Setting of Break Control Conditions
PC Break