R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 275

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.6.3
This section describes the basic timing when the data is specified as big endian.
(1)
Figures 9.15 to 9.17 show the bus timing of 16-bit 2-state access space.
When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even
addresses access, and the lower byte data bus (D7 to D0) is used for odd addresses. No wait cycles
can be inserted.
Figure 9.15 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address)
16-Bit 2-State Access Space
Basic Timing
Read
Write
DACK or EDACK
Address
CSn
AS
RD
D15 to D8
D7 to D0
LHWR
LLWR
D15 to D8
D7 to D0
BS
RD/WR
Notes:
1. n = 0 to 7
2. When RDNn = 0
3. When DKC and EDKC = 0
T
1
Bus cycle
High level
High-Z
Valid
Rev. 2.00 Oct. 21, 2009 Page 241 of 1454
T
2
Invalid
Valid
Section 9 Bus Controller (BSC)
REJ09B0498-0200

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