R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 57

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Classification
Bus control
Pin Name
CS0
CS1
CS2-A/CS2-B
CS3
CS4-A/CS4-B
CS5-A/CS5-B/
CS5-D
CS6-A/CS6-B/
CS6-D
CS7-A/CS7-B
WAIT
RAS
CAS
WE
OE/CKE
LUCAS
LLCAS
DQMLU
DQMLL
I/O
Output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Description
Select signals for areas 0 to 7.
Requests wait cycles in access to the external space.
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Row address strobe signal for the DRAM when area 2
is specified as the DRAM interface space
Row address strobe signal for the synchronous DRAM
when area 2 is specified as the synchronous DRAM
interface space
Column address strobe signal for the synchronous
DRAM when area 2 is specified as the synchronous
DRAM interface space
Write enable signal for the DRAM space
Synchronous DRAM write enable signal when area 2 is
specified as the synchronous DRAM interface space
Output enable signal for the DRAM interface space
Clock enable signal for the synchronous DRAM
interface space
Upper column address strobe signal for the 16-bit
DRAM interface space
Lower column address strobe signal for the 16-bit
DRAM interface space
Column address strobe signal for the 8-bit DRAM
interface space
Upper data mask enable signal for the 16-bit
synchronous DRAM interface space
Lower data mask enable signal for the 16-bit
synchronous DRAM interface space
Data mask enable signal for the 8-bit synchronous
DRAM interface space
Rev. 2.00 Oct. 21, 2009 Page 23 of 1454
Section 1 Overview
REJ09B0498-0200