R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 522

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
(2)
Burst Mode
In burst mode, once the EXDMAC acquires the bus mastership, it continues transferring data,
without releasing the bus mastership, until the transfer end condition is satisfied. In burst mode,
once transfer is started it is not interrupted even if there is a transfer request for another channel
with higher priority. When the burst mode channel finishes its transfer, it releases the bus
mastership in the next cycle in the same way as in cycle steal mode. However, when the EBCCS
bit in BCR2 of the bus controller is set to 1, the EXDMAC can temporarily release the bus
mastership for another bus master when an external access request is generated from another bus
master.
In block transfer mode and cluster transfer mode, the setting of burst mode is invalid (one-block or
one-cluster transfer is processed in the same way as in burst mode). The EXDMAC always
operates in cycle steal mode.
When the DTE bit is cleared to 0 in EDMDR, EXDMA transfer is halted. However, EXDMA
transfer is executed for all transfer requests generated within the EXDMAC until the DTE bit is
cleared to 0. If a transfer size error interrupt, a repeat size end interrupt, or extended repeat area
overflow interrupt is generated, the DTE bit is cleared to 0 and transfer is terminated.
Figure 11.14 shows an example of the timing in burst mode.
Bus cycle
CPU
CPU
EXDMAC
EXDMAC
EXDMAC
CPU
CPU
CPU cycle not generated
Figure 11.14 Example of Timing in Burst Mode
11.5.5
Extended Repeat Area Function
The EXDMAC has a function for designating an extended repeat area for source addresses and/or
destination addresses. When an extended repeat area is designated, the address register values
repeat within the range specified as the extended repeat area. Normally, when a ring buffer is
involved in a transfer, an operation is required to restore the address register value to the buffer
start address each time the address register value becomes the last address in the buffer (i.e. when
ring buffer address overflow occurs). However, if the extended repeat area function is used, the
operation that restores the address register value to the buffer start address is processed
automatically within the EXDMAC.
The extended repeat area function can be set independently for the source address register
(EDSAR) and the destination address register (EDDAR).
Rev. 2.00 Oct. 21, 2009 Page 488 of 1454
REJ09B0498-0200