R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 618

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Data Transfer Controller (DTC)
Table 12.10 Number of Cycles Required for Each Execution State
[Legend]
m: Number of wait cycles 0 to 7 (For details, see section 9, Bus Controller (BSC).)
The number of execution cycles is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
12.5.10 DTC Bus Release Timing
The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The
DTC releases the bus after a vector read, transfer information read, a single data transfer, or
transfer information writeback. The DTC does not release the bus during transfer information
read, single data transfer, or transfer information writeback.
12.5.11 DTC Priority Level Control to the CPU
The priority of the DTC activation sources over the CPU can be controlled by the CPU priority
level specified by bits CPUP2 to CPUP0 in CPUPCR and the DTC priority level specified by bits
DTCP2 to DTCP0. For details, see section 7, Interrupt Controller.
Rev. 2.00 Oct. 21, 2009 Page 584 of 1454
REJ09B0498-0200
Object to be Accessed
Bus width
Access cycles
Execution
status
Number of execution cycles = I
Vector read S
Transfer information read S
Transfer information write S
Byte data read S
Word data read S
Longword data read S
Byte data write S
Word data write S
Longword data write S
Internal operation S
I
L
M
L
M
N
L
M
J
k
On-Chip
RAM
32
1
1
1
1
1
1
1
1
1
1
•
S
I
On-Chip
ROM
32
1
1
1
1
1
1
1
1
1
1
+ Σ (J
•
8
2
⎯ ⎯
⎯ ⎯
⎯ ⎯
2
4
8
2
4
8
S
On-Chip I/O
J
Registers
+ K
16
2
2
2
4
2
2
4
•
S
32
2
⎯
⎯
⎯
2
2
2
2
2
2
K
+ L
1
•
2
8
8
8
2
4
8
2
4
8
S
L
+ M
8
3
12 + 4m
12 + 4m
12 + 4m
3 + m
4 + 2m
12 + 4m
3 + m
4 + 2m
12 + 4m
External Devices
•
S
M
) + N
2
4
4
4
2
2
4
2
2
4
•
S
16
N
3
6 + 2m
6 + 2m
6 + 2m
3 + m
3 + m
6 + 2m
3 + m
3 + m
6 + 2m