R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 545

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
11.5.11 Bus Cycles in Single Address Mode
(1)
In single address mode, the bus is released after one byte, word, or longword has been transferred
in response to one transfer request. While the bus is released, one or more CPU, DMAC, or DTC
bus cycles are initiated.
Figure 11.34 shows an example of transfer when ETEND output is enabled, and byte-size, single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
Single Address Mode (Read in Cycle Steal Mode)
Figure 11.34 Example of Single Address Mode (Byte Read) Transfer
Address bus
RD
EDACK
ETEND
released
Bus
EXDMA read
release
Bus
EXDMA read
release
Bus
EXDMA read
Rev. 2.00 Oct. 21, 2009 Page 511 of 1454
Section 11 EXDMA Controller (EXDMAC)
release
Bus
EXDMA read
Last transfer
cycle
release
Bus
REJ09B0498-0200

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