R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 889

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.3.3
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
but not by the WDT internal reset signal caused by WDT overflows.
Note:
Bit
7
6
5
4 to 0
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to this bit, to clear the flag.
*
Bit Name
WOVF
RSTE
⎯
⎯
Reset Control/Status Register (RSTCSR)
Only 0 can be written to this bit, to clear the flag.
R/(W)*
WOVF
7
0
Initial
Value
0
0
0
All 1
RSTE
R/W
6
0
R/W
R/(W)* Watchdog Timer Overflow Flag
R/W
R/W
R
R/W
⎯
5
0
Reset Enable
Reserved
Description
This bit is set when TCNT overflows in watchdog timer
mode. This bit cannot be set in interval timer mode, and
only 0 can be written.
[Setting condition]
When TCNT overflows (changed from H'FF to H'00) in
watchdog timer mode
[Clearing condition]
Reading RSTCSR when WOVF = 1, and then writing 0 to
WOVF
Specifies whether or not this LSI is internally reset if
TCNT overflows during watchdog timer operation.
0: LSI is not reset even if TCNT overflows (Though this
1: LSI is reset if TCNT overflows
Although this bit is readable/writable, reading from or
writing to this bit does not affect operation.
Reserved
These are read-only bits and cannot be modified.
LSI is not reset, TCNT and TCSR in WDT are reset)
⎯
R
4
1
⎯
R
3
1
Rev. 2.00 Oct. 21, 2009 Page 855 of 1454
Section 18 Watchdog Timer (WDT)
⎯
R
2
1
⎯
R
1
1
REJ09B0498-0200
⎯
R
0
1