R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 333

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus Controller (BSC)
(3)
Refresh and All-Module Clock Stop Mode
This LSI is entered in all-module clock stop mode by the following operation: Stop the clocks of
all on-chip peripheral modules by setting the ACSE bit in MSTPCR to 1 (MSTPCRA, MSTPCRB
= H'FFFFFFFF) or run only the 8-bit timer (MSTPCRA, MSTPCRB = H'F[C to F]FFFFFF), then
execute the SLEEP instruction to enter the sleep mode.
In all-module clock stop mode, clocks for the bus controller and I/O ports are stopped. Since the
clock for the bus controller is stopped, a CBR refresh cycle cannot be performed. When external
DRAM is used and the contents of the DRAM in sleep mode should be held, clear the ACSE bit in
MSTPCE to 0.
For details, see section 28.2.2, Module Stop Control Registers A and B (MSTPCRA and
MSTPCRB).
9.10.13 DRAM Interface and Single Address Transfer by DMAC and EXDMAC
When fast-page mode (BE = 1) is set for the DRAM space, either fast-page access or full access
can be selected, by the setting of bits DDS and EDDS in DRAMCR, for the single address transfer
by the DMAC or EXDMAC where the DRAM space is specified as the transfer source or
destination. At the same time, the output timings of the DACK, EDACK and BS signals are
changed. When BE = 0, full access to the DRAM space is performed by single address transfer
regardless of the setting of bits DDS and EDDS. However, the output timing of the DACK,
EDACK and BS signals can be changed by the setting of bits DDS and EDDS.
The assertion timing of the DACK and EDACK signal can be changed by bits DKC and EDKC in
BCR1.
Rev. 2.00 Oct. 21, 2009 Page 299 of 1454
REJ09B0498-0200

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