R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 315

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

To ensure the row address hold time or read access time, one to three of Trw cycles in which the
row address output is retained can be inserted between the Tr and Tc1 cycles. The RAS signal is
driven low in the Tr cycle and the column address is output in the Tc1 cycle. Set the bit according
to the DRAM to be used and the frequency of this LSI so that the row address hold time to the
rising edge of the RAS signal is ensured.
Figure 9.41 shows an access timing example when one Trw cycle is specified.
Figure 9.41 Access Timing Example when One Trw Cycle is Specified (RAST=0, CAST=0)
Read
Write
Address bus
Data bus
OE (RD)
Data bus
OE (RD)
RD/WR
LUCAS
LLCAS
RAS
WE
WE
BS
Bφ
T
p
Row address
T
r
High
High
T
rw
Rev. 2.00 Oct. 21, 2009 Page 281 of 1454
T
Column address
c1
Section 9 Bus Controller (BSC)
T
c2
REJ09B0498-0200