R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 186

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Interrupt Controller
7.6
The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt
control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt
control mode is selected by INTCR. Table 7.3 shows the differences between interrupt control
mode 0 and interrupt control mode 2.
Table 7.3
Interrupt
Control
Mode
0
2
7.6.1
In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit in CCR of
the CPU. Figure 7.3 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the
2. If the I bit in CCR is set to 1, NMI is accepted, and other interrupt requests are held pending. If
3. For multiple interrupt requests, the interrupt controller selects the interrupt request with the
4. When the CPU accepts the interrupt request, it starts interrupt exception handling after
5. The PC and CCR contents are saved to the stack area during the interrupt exception handling.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
Rev. 2.00 Oct. 21, 2009 Page 152 of 1454
REJ09B0498-0200
interrupt request is sent to the interrupt controller.
the I bit is cleared to 0, an interrupt request is accepted.
highest priority, sends the request to the CPU, and holds other interrupt requests pending.
execution of the current instruction has been completed.
The PC contents saved on the stack is the address of the first instruction to be executed after
returning from the interrupt handling routine.
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Interrupt Control Modes and Interrupt Operation
Interrupt Control Mode 0
Interrupt Control Modes
Priority
Setting
Register
Default
IPR
Interrupt
Mask Bit
I
I2 to I0
Description
The priority levels of the interrupt sources are fixed
default settings.
The interrupts except for NMI is masked by the I bit.
Eight priority levels can be set for interrupt sources
except for NMI with IPR.
8-level interrupt mask control is performed by bits I2 to I0.