R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 48

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 Overview
Rev. 2.00 Oct. 21, 2009 Page 14 of 1454
REJ09B0498-0200
Figure 1.4 Pin Assignments (LGA-145: H8SX/1665 Group and H8SX/1665M Group)
G
M
A
B
C
D
E
F
H
K
N
J
L
Notes: 1.
/PK5*
/PK0*
/PJ3*
/PJ2*
/PJ0*
MD2
PM2
PD3
PD2
PD0
PB2
PB3
PF4
PF1
PE5
PE0
PB1
Vcc
1
1
2.
3.
1
1
1
1
1
In single-chip mode ports D and E can be used (initial state). Pin functions are selectable by setting the
This pin is an on-chip emulator enable pin. Drive this pin low for the connection in normal operating mode.
The on-chip emulator function is enabled by driving this pin high. When the on-chip emulator is in use, the
P62, P63, P64, P65, and WDTOVF pins are dedicated pins for the on-chip emulator. For details on a connection
example with the E10A, see E10A Emulator User's Manual.
PCJKE bit in PFCRD. Ports D and E are enabled when PCJKE = 0 (initial value) and ports J and K are
enabled when PCJKE = 1. In external extended mode, only ports D and E can be used.
The NC (no-connection) pin should be left open.
/PK6*
/PK4*
/PK1*
/PJ5*
/PJ1*
PM1
PB0
PB7
PE6
PE4
PE1
PD5
PD1
PM3
PF5
PF2
PA7
Vss
2
2
1
1
1
1
1
EMLE*
/PK7*
/PK3*
/PJ7*
/PJ4*
DrVcc
PM0
PD7
PD4
PF6
PE7
PE3
PM4
Vcc
Vss
Vss
Vss
3
3
1
1
1
1
2
/PK2*
/PJ6*
USD
VBUS
USD-
PD6
PA4
PA2
PA6
PF7
PF3
PF0
PE2
Vcc
Vss
4
4
+
1
1
MD_CLK
NC*
DrVss
MD3
PA1
PA5
PA3
Vcc
Vss
5
5
3
(Upper perspective view)
MD1
PB6
PB5
PA0
P21
P24
P20
P22
6
6
LGA-145
PB4
P57
P54
P56
P25
P32
P23
P30
7
7
AVcc
AVss
Vref
P55
P26
P33
P31
P27
8
8
PH0
P50
P52
P51
P53
P34
NMI
Vcc
9
9
MD0
PC3
PC2
PH2
PH1
PH3
P65
P17
P14
Vcc
Vc
Vss
PI7
10
10
L
PLLVss
PH4
PH5
P64
P63
P35
P16
P15
P13
P11
P10
PI4
PI2
11
11
PLLVcc
OSC1
XTAL
PH7
PH6
P62
P36
P12
Vss
Vss
Vss
PI5
PI3
12
12
WDTOVF
EXTAL
OSC2
STBY
RES
P61
P60
P37
Vss
Vcc
PI6
PI1
PI0
13
13
M
C
D
G
H
N
A
B
E
F
K
L
J