R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 609

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.5.2
By setting the RRS bit of DTCCR, the vector address read and transfer information read can be
skipped. The current DTC vector number is always compared with the vector number of previous
activation. If the vector numbers match when RRS = 1, a DTC data transfer is performed without
reading the vector address and transfer information. If the previous activation is a chain transfer,
the vector address read and transfer information read are always performed. Figure 12.6 shows the
transfer information read skip timing.
To modify the vector table and transfer information, temporarily clear the RRS bit to 0, modify the
vector table and transfer information, and then set the RRS bit to 1 again. When the RRS bit is
cleared to 0, the stored vector number is deleted, and the updated vector table and transfer
information are read at the next activation.
Clock
DTC activation
request
DTC request
Transfer
information
read skip
Address
Note: Transfer information read is skipped when the activation sources of (1) and (2) (vector numbers) are the same while RRS = 1.
Transfer Information Read Skip Function
(1)
Figure 12.6 Transfer Information Read Skip Timing
Vector read
Transfer information
read
R
transfer
Data
W
Transfer information
write
Section 12 Data Transfer Controller (DTC)
Rev. 2.00 Oct. 21, 2009 Page 575 of 1454
(2)
R
transfer
Data
W
Transfer information
REJ09B0498-0200
write

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