R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 971

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.7.6
Data transmission in smart card interface mode (except in block transfer mode) is different from
that in normal serial communication interface mode in that an error signal is sampled and data can
be re-transmitted. Figure 19.29 shows the data re-transfer operation during transmission.
1. If an error signal from the receiving end is sampled after one frame of data has been
2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is
3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1.
4. In this case, one frame of data is determined to have been transmitted including re-transfer, and
Figure 19.31 shows a sample flowchart for transmission. All the processing steps are
automatically performed using a TXI interrupt request to activate the DTC or DMAC. In
transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a
TXI interrupt request if the TIE bit in SCR has been set to 1. This activates the DTC or DMAC by
a TXI request thus allowing transfer of transmit data if the TXI interrupt request is specified as a
source of DTC or DMAC activation beforehand. The TDRE and TEND flags are automatically
cleared to 0 at data transfer by the DTC or DMAC. If an error occurs, the SCI automatically re-
transmits the same data. During re-transmission, TEND remains as 0, thus not activating the DTC
or DMAC. Therefore, the SCI and DTC or DMAC automatically transmit the specified number of
bytes, including re-transmission in the case of error occurrence. However, the ERS flag is not
automatically cleared; the ERS flag must be cleared by previously setting the RIE bit to 1 to
enable an ERI interrupt request to be generated at error occurrence.
When transmitting/receiving data using the DTC or DMAC, be sure to set and enable the DTC or
DMAC prior to making SCI settings. For DTC or DMAC settings, see section 12, Data Transfer
Controller (DTC) and section 10, DMA Controller (DMAC).
transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the
RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled.
re-transferred from TDR to TSR allowing automatic data retransmission.
the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in
SCR is set to 1. Writing transmit data to TDR starts transmission of the next data.
Data Transmission (Except in Block Transfer Mode)
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
Rev. 2.00 Oct. 21, 2009 Page 937 of 1454
REJ09B0498-0200