R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 393

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
DQMLU, DQMLL
[1] A low level of the BREQ signal is sampled at the rising edge of the Bφ signal.
[2] The PALL command is issued.
[3] The bus control signals are driven high at the end of the external access cycle. It takes two cycles or
[4] The BACK signal is driven low, releasing bus to the external bus master.
[5] The BREQ signal state sampling is continued in the external bus released state.
[6] A high level of the BREQ signal is sampled.
[7] The BACK signal is driven high, ending external bus release cycle after one cycle.
[8] When the external space is accessed by an internal bus master or a refresh cycle is requested during external
[9] Normally the BREQO signal goes high at the rising edge of the BACK signal.
Precharge-sel
Figure 9.103 Bus Released State Transition Timing (SRAM Interface is Used)
more after the low level of the BREQ signal is sampled.
bus released while the BREQOE bit is set to 1, the BREQO signal goes low.
Address bus
SDRAMφ
Data bus
BREQO
BREQ
BACK
CKE
RAS
CAS
CS2
WE
[1]
access cycle
NOP
T
External
1
T
2
[2]
PALL NOP
[3]
[4]
External bus released state
[5]
[8]
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
[6]
Rev. 2.00 Oct. 21, 2009 Page 359 of 1454
[9]
NOP
Section 9 Bus Controller (BSC)
[7]
CPU cycle
REJ09B0498-0200

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