R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1326

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 28 Power-Down Modes
28.11
Output of the φ clock (Bφ/SDφ) can be controlled by bits PSTOP1 and PSTOP0 in SCKCR, and
DDR for the corresponding port. Bits PSTOP1 control the Bφ clock output on the PA7 pin. Bit
PSTOP0 controls the SDφ clock output on the PB7 pin. When bit PSTOP1 is set to 1, the Bφ clock
output stops at the end of the bus cycle and goes high. In the same way, bit PSTOP0 drives the
SDφ clock output on the PB7 pin high. When DDR for the PA7 pin is cleared to 0, the Bφ clock
output is disabled and the pin becomes an input port. When the SDRAM interface is disabled, the
PB7 pin can be used as I/O port.
Tables 28.4 and 28.5 show the states of the φ pin in each processing state.
Table 28.4 φ Pin (PA7) State in Each Processing State
[Legend]
x = Don't care
Table 28.5 φ Pin (PB7) State in Each Processing State (When SDRAM Interface is
Rev. 2.00 Oct. 21, 2009 Page 1292 of 1454
REJ09B0498-0200
DDR
0
1
1
PSTOP0
0
1
Register Setting Value
Register Setting Value
φ Clock Output Control
PSTOP1
x
0
1
Enabled)
Normal
Operating
Mode
Hi-Z
Bφ output
High
Normal
Operating
Mode
SDφ output
High
Sleep
Mode
Hi-Z
Bφ output Bφ output
High
Sleep
Mode
SDφ
output
High
All-
Module-
Clock-Stop
Mode
Hi-Z
High
All-
Module-
Clock-Stop
Mode
SDφ output High
High
OPE = 0
Hi-Z
High
High
OPE = 0
High
Standby Mode
Standby Mode
Software
Software
OPE = 1
Hi-Z
High
High
OPE = 1
High
High
IOKEEP = 0
Hi-Z
High
High
IOKEEP = 0
High
High
Deep Software
Deep Software
Standby Mode
Standby Mode
IOKEEP = 1
Hi-Z
High
High
IOKEEP = 1
High
High
Hardware
Standby
Mode
Hi-Z
Hi-Z
Hi-Z
Hardware
Standby
Mode
Hi-Z
Hi-Z

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