R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 964

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
19.6.5
Figure 19.23 shows a sample flowchart for simultaneous serial transmit and receive operations.
After initializing the SCI, the following procedure should be used for simultaneous serial data
transmit and receive operations. To switch from transmit mode to simultaneous transmit and
receive mode, after checking that the SCI has finished transmission and the TDRE and TEND
flags are set to 1, clear the TE bit to 0. Then simultaneously set both the TE and RE bits to 1 with
a single instruction. To switch from receive mode to simultaneous transmit and receive mode,
after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking that
the RDRF bit and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set
both the TE and RE bits to 1 with a single instruction.
Rev. 2.00 Oct. 21, 2009 Page 930 of 1454
REJ09B0498-0200
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous
Mode) (SCI_0, 1, 2, and 4 only)
[3]
No
No
Read receive data in RDR and
clear RDRF flag in SSR to 0
Clear ORER flag in SSR to 0
Read ORER flag in SSR
Read RDRF flag in SSR
Clear RE bit in SCR to 0
Overrun error processing
Figure 19.22 Sample Serial Reception Flowchart
All data received
Error processing
Start reception
Initialization
ORER = 1
RDRF = 1
<End>
<End>
Yes
Yes
No
(Continued below)
Error processing
Yes
[2]
[1]
[3]
[4]
[5]
[1] SCI initialization:
[2] [3] Receive error processing:
[4] SCI state check and receive data
[5] Serial reception continuation
The RxD pin is automatically
designated as the receive data input
pin.
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Reception cannot be resumed if the
ORER flag is set to 1.
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0. Transition of the RDRF flag from
0 to 1 can also be identified by an RXI
interrupt.
procedure:
To continue serial reception, before
the MSB (bit 7) of the current frame is
received, reading the RDRF flag,
reading RDR, and clearing the RDRF
flag to 0 should be finished. However,
the RDRF flag is cleared automatically
when the DMAC or DTC is initiated by
a receive data full interrupt (RXI) and
reads data from RDR.

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