R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 322

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
9.10.11 Burst Access Operation
Besides an accessing method in which this LSI outputs a row address every time it accesses the
DRAM (called full access or normal access), some DRAMs have a fast-page mode function in
which fast speed access can be achieved by modifying only a column address with the same row
address output (burst access) when consecutive accesses are made to the same row address.
The fast-page mode (burst access) can be specified when the BE bit in DRAMCR is set to one,
(1)
Figures 9.48 and 9.49 show operation timing of the fast-page mode.
When access cycles to the DRAM space are continued and the row addresses of the consecutive
two cycles are the same, output cycles of the CAS and column address signals follow. The row
address bits to be compared are decided by bits MXC1 and MXC0 in DRAMCR.
Wait cycles can be inserted during a burst access. The method and timing of the wait insertion are
the same as that of full access mode. For details, see section 9.10.9, Wait Control.
Rev. 2.00 Oct. 21, 2009 Page 288 of 1454
REJ09B0498-0200
Burst Access (Fast-Page Mode) Operation Timing
Figure 9.47 Example of Connection for Control with Two CAS Signals
(Address shifted by 11 bits)
This LSI
D15 to D0
RD (OE)
LUCAS
LLCAS
RAS
A11
A10
WE
A9
A8
A7
A6
A5
A4
A3
A2
A1
Two CAS signals used 64-Mbit DRAM
(4 Mwords × 16 bits)
11-bit column address
RAS
UCAS
LCAS
WE
OE
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15 to D0
Row address input:
Column address input: A10 to A0
A10 to A0